Nonvolatile memory (NVM) is a form of memory widely utilized in the microelectronics industry. To date, the dominant form of NVM has been flash (e.g., NAND, NOR, etc.). Many alternative NVM technologies are under development for next generation devices. One of the considerations for next-gen NVM technology is how readily it can be integrated with CMOS logic circuitry. Embedded non-volatile memory (e-NVM) is a non-volatile memory integrated on-chip with logic devices (e.g., fabricated in CMOS technology). e-NVM is distinct from stand-alone NVM where the memory array is fabricated on a substrate dedicated to the memory. Embedded NVM advantageously eliminates the need for inter-chip communication between a processor and off-chip memory, and consequently enables high-speed data access and wide bus-width capability for any logic implemented on-chip along with the e-NVM (e.g., cores of a CPU, graphics processor execution unit, etc.).
Of the various NVM technologies, resistive memory technologies continue to show significant promise both for discrete and e-NVM applications. In a resistive memory, such as resistive random-access memory (ReRAM or RRAM), the thin film memory stack is generally a two-terminal device of the form illustrated in FIG. 1A. For thin film resistive memory material stack 101, a comparatively insulating memory material 115 capable of non-volatile switching is disposed between two relatively more conductive electrodes 105, 130. The memory material can switch between two different non-volatile states: a high-resistance state (HRS), which may be representative of an “off” or 0 state; and a low-resistance state (LRS), which may be representative of an “on” or 1 state. Typically, a reset process is used to switch the ReRAM device to the HRS using a reset voltage, and a set process is used to switch the ReRAM device to the LRS using a set voltage. To reduce off-state leakage of a resistive memory array, a resistive memory bitcell often includes an access transistor (1T) or a thin film selector element (1S) along with the resistive memory element (1R).
Forming voltage and cell endurance are two important metrics for thin film resistive memory technology. The forming voltage is to impart the memory element with the ability to switch. Because of the limited operating voltage found in state of the art CMOS (e.g., Vcc<0.9V), achieving a sufficiently low forming voltage is particularly challenging for e-NVM applications. As further depicted in FIG. 1A, defects 116 are engineered in memory material 115 to enable modulation of electrical conduction through the film thickness. Defects 116 are currently thought to be primarily oxygen vacancies. Addition of an oxygen exchange layer (e.g., Ti cap 121) between an electrode and the memory element has been found to promote creation of oxygen vacancies, and lower forming voltages as further illustrated in FIG. 1B. An oxygen exchange layer of Ti, Hf, Zr, or Ta has been typically utilized for the various binary and ternary metal oxides evaluated for the switchable memory material.
Memory cell reliability is generally characterized with a number of set/reset cycles. Historically, resistive memory cell reliability/endurance has been poor and although it has gradually improved over the last decade it remains in the range of 1011-1012 set/reset cycles, which may limit the use cases/applications for the technology.